The present disclosure relates generally to semiconductor manufacture and, more particularly, to a method for patterning a photosensitive layer in semiconductor manufacture.
Photolithography is frequently used for forming the components of integrated circuits (IC). Generally, an exposure tool includes a photomask or reticle, through which light beams pass through and are focused by a projection lens onto a wafer, resulting in an image of device features in a photosensitive layer such as a photoresist layer formed on the wafer. There has been a continued increase in the density of devices that can be placed on a chip and as a result, the printing of device feature patterns with an extremely small pitch is required. However, there is a minimum pitch printing resolution limit that is determined by the wavelength of the light beam and the numerical aperture of the exposure tool. The pitch is the distance from one device feature to an adjacent device feature. If the pitch becomes too small, the projected image may be distorted by so called “proximity effects” that are associated with the diffraction of light. One method for forming such device features includes two photolithography processes and two etching processes. For example, a first mask is formed to provide a first pattern with substantially linear features. The substrate is then etched according to this first pattern to form substantially linear features. The first mask is then removed from the substrate. A second mask may then be formed to provide a second pattern for gaps in the previously formed substantially linear features. The substrate may then be etched according to this second pattern. The numerous steps required add costs to the fabrication including, for example, increased complexity of the processing and increased cycle time.
Therefore, what is needed is a simple and cost-effective method for patterning a photosensitive layer in semiconductor manufacture for process technologies of 45 nm and below.